The present invention relates to methods of manufacturing flash memory devices, and more particularly to a method of manufacturing a flash memory device capable of improving programming speed by increasing the phosphorous concentration of the polysilicon layer used as the control gate, but not reducing coupling ratio.
In general, a typical flash memory cell is embodied by forming a gate and source/drain. The gate is comprised of a sequentially stacked structure of tunnel oxide, a floating gate, a dielectric layer, and a control gate at predetermined regions over a semiconductor substrate. The source/drain is formed at both sides of the gate on the semiconductor substrate. Such a flash memory cell is programmed or erased by injecting or emitting electrons to the floating gate, thereby generating hot carriers through a lateral surface of the drain. In addition, the program operation is performed by injecting hot carriers into the floating gate through the tunnel oxide. The erase operation is performed by emitting electrons from the floating gate according to a Fowler-Nordheim (F-N) tunneling mechanism by inducing a high electric field between the source and floating gate, or the bulk and floating gate.
In order to perform the program and erase operations of the flash memory cell, it is necessary to apply a high voltage to all gates. However, there are several limits in the flash memory cell in conditions of low voltage. This is because a bias is not directly applied to the floating gate, but applied only to the control gate. In other words, voltage drops across the dielectric layer between the control gate and the floating gate. This voltage drop depends on the thickness and the junction area of the dielectric layer.
A capacitance rate is known as a “coupling ratio”. If coupling ratio is “1,” this means that a bias applied to the control gate is applied to the floating gate as it is. Consequently, the smaller the coupling ratio is, the higher a bias applied to the control gate to drive flash memory cells needs to be. The coupling ratio of flash memory cells are largely influenced by the thickness of dielectric layers, junction area between dielectric layers and the gates, and phosphorous doping concentration of polysilicon used as control gates.
In cases where phosphorous doping concentration of polysilicon is increased so as to improve programming speed, the thickness of dielectric layers is increased. Accordingly, coupling ratio is reduced, thereby decreasing programming speed. In contrast, if phosphorous doping concentration of polysilicon is decreased, electrons are depleted so that programming speed is reduced due to a variation of the coupling ratio. Therefore, there is a need for a new doping process in polysilicon used as control gates in order to improve programming speed.